This nonprovisional application claims priority under 35 U.S.C. xc2xa7119(a) on Patent Application No. 2000-80432 filed in Korea on Dec. 22, 2000, which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to memory devices; and, more particularly, to a memory cell sensing circuit of a nonvolatile memory device, e.g., a flash memory device, capable of enhancing its sensing speed.
2. Description of the Background Art
As a flash memory device goes to large-scale integration, its operating voltage gets progressively lower. As a result, when sensing flash memory cells, the sensing current becomes very small. Thus, a problem arises in that it is difficult to sense a memory cell through which a lot of current flows, i.e., a memory cell having a xe2x80x981xe2x80x99 state.
To overcome the drawback, there has been introduced a method for increasing an output gain of a sense amplifier.
Referring to FIG. 1, there is shown a schematic diagram of a conventional flash memory cell sensing circuit.
A first resistor R11 is connected between a supply voltage node Vcc and a first node Q11 being a sensing node of a main cell M11. A first NMOS transistor N11 and the main cell M11 are positioned between the first node Q11, and a ground node Vss. The first NMOS transistor N11 operates in response to an output of a first inverter I11 inverting the potential of a bit line BL1 of the main cell M11. Further, the main cell M11 operates according to a voltage provided through a word line WL.
Meanwhile, a second resistor R12 is attached between the supply voltage node Vcc and a second node Q12, being a sensing node of a reference cell M12. A second NMOS transistor N12 and the reference cell M12 are located between the second node Q12 and the ground node Vss. The second NMOS transistor N12 operates under the control of an output of a second inverter I12 inverting the potential of a bit line BL2 of the reference cell M12. Moreover, the reference cell M12 operates in response to a voltage supplied through the word line WL.
A sense amplifier 11 compares the potential of the first node Q11 being the potential of the main cell M11 and the potential of the second node Q12 being the potential of the reference cell M12, and outputs a comparison result as a sensing output signal SAOUT.
As described above, since the conventional flash memory cell sensing circuit employs a circuit for sensing a state of the main cell, and that being for sensing a state of the reference cell, whose configurations are identical to each other, the state of the main cell can be sensed by the sense amplifier comparing the potential of the main cell on the basis of the potential of the reference cell, and outputting a sensing output signal.
Hereinafter, the operation of the conventional flash memory cell sensing circuit will be explained with reference to the timing diagram illustrated in FIG. 2.
Before a sensing enable signal SAEN having an enable state is coupled to sense a cell state, the bit line BL1 of the main cell M11 and the bit line BL2 of the reference cell M12 are precharged. That is, the supply voltage Vcc is provided to the first node Q11 through the first resistor R11, and the potential of the first node Q11 is transferred to the bit line BL1 of the main cell M11 through the first NMOS transistor N11, so as to precharge the bit line BL1. The first NMOS transistor N11 is turned on since the potential of the bit line BL1 has an initial low state and, thus, the first inverter I11 produces an output having a high state. Then, if the potential of the bit line BL1 becomes higher than a certain level, the first NMOS transistor N11 is turned off in response to its input signal being inverted to a low state by the first inverter I11. As a result, the potential of the bit line BL1 maintains the certain level. The bit line BL2 of the reference cell M12 is also precharged in the same manner as used in precharging the bit line BL1 of the main cell M11.
As depicted above, after the bit line BL1 of the main cell M11 and the bit line BL2 of the reference cell M12 are precharged, if the sensing enable signal SAEN having the enable state, e.g., a high state, is inputted to the memory cell sensing circuit and a word line voltage is provided to the main cell M11, the sensing operation for the main cell M11 is performed. That is to say, if the sensing enable signal SAEN of the enable state is inputted, the potential of the second node Q12, i.e., the potential of the reference cell M12, gradually decreases, and then maintains a constant potential after a prescribed time as indicated by A. In the meantime, the potential of the first node Q11 is changed according to the state of the main cell M11. Namely, the potential of the bit line BL1 maintaining the precharged potential before the sensing enable signal SAEN of the enable state is inputted, becomes lower as the word line voltage is provided to the main cell M11 and, then, ascends again depending on the supply voltage Vcc continuously provided to the circuit, as indicated by B. Next, if the main cell M11 has a xe2x80x980xe2x80x99 state, the potential of the first node Q11 rises as an amount of current flowing to the ground node Vss through the main cell M11 becomes smaller. On the other hand, if the main cell M11 has a xe2x80x981xe2x80x99 state, the potential of the first node Q11 becomes lower since the current is continuously passed to the ground node Vss through the main cell M11. Accordingly, the sensing output signal SAOUT of the sense amplifier 11 is changed and the state of the main cell M11 is sensed.
In the conventional flash memory cell sensing circuit described above, in a case of the main cell having the xe2x80x980xe2x80x99 state, the sensing output signal maintains its state after the sensing, without being changed. On the other hand, in a case of the main cell having the xe2x80x981xe2x80x99 state, the sensing output signal is changed from the xe2x80x980xe2x80x99 state in which current does not flow to the xe2x80x981xe2x80x99 state as the current starts to flow. As a result, the final sensing speed of the device determined by the xe2x80x981xe2x80x99 state sensing is deteriorated and, ultimately, it is inevitable for the sensing speed to be directly affected by the cell current.
Furthermore, in general, the conventional flash memory cell sensing circuit uses a resistor having a high resistance in order to improve the sensing speed. In this case, since the voltage of the sensing node is substantially low during precharging the bit line, the current cannot be provided to the bit line anymore, resulting in making the time required to precharge the bit line longer, and diminishing the sensing speed.
It is, therefore, a primary object of the present invention to provide a memory cell sensing circuit capable of enhancing a sensing speed by reducing a time required in changing a cell sensing output of a xe2x80x980xe2x80x99 state to that of a xe2x80x981xe2x80x99 state.
In accordance with the present invention, there is provided a memory cell sensing circuit comprising:
a main cell and a reference cell;
a first loading unit for providing a preset voltage to a sensing node of the main cell;
a second loading unit for supplying a prescribed voltage to a sensing node of the reference cell;
a first switching unit for adjusting the potential of the sensing node of the main cell;
a second switching unit for controlling the potential of the sensing node of the reference cell;
a main cell bit line voltage controlling unit for adjusting the potential of a bit line of the main cell;
a reference cell bit line voltage controlling unit for adjusting the potential of a bit line of the reference cell; and
a sense amplifier for sensing a state of the main cell by comparing the potential of the sensing node of the main cell and that of the sensing node of the reference cell.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.